The present invention relates generally to sense amplifiers, and specifically, to low power sense amplifiers for CMOS memories.
Most CMOS memories use a differential type sense amplifier as illustrated in FIG. 1. Advantages of the differential type sense amplifier are its high speed and its sensitivity to the small voltage changes between the bit lines. However, a major drawback of this type of amplifier is its high current consumption. This makes the use of a differential type sense amplifier undesirable in a CMOS memory, since a main advantage of CMOS technology is its low power comsumption. This problem is exacerbated for large word memories where each bit in a word requires a sense amplifier.
Some CMOS memories use cross-coupled sense amplifier latches as illustrated in FIG. 2 which do not use current in some situations. However, these cross-coupled sense amplifier latches are considerably slower than the differential type sense amplifier.
Thus, an object of the present invention is to provide a sense amplifier for use in a memory device which has low power consumption, yet is not significantly slower than the high power differential type sense amplifier.
Another object of the present invention is to provide a sense amplifier which is CMOS compatible.
A further object of the present invention is to provide a sense amplifier which consumes relatively little power, but has isolation between the data and bit lines.
This object and other objects of the present invention are attained by providing a sense amplifier with bit line sensors for sensing the voltage levels of a pair of bit lines, and a latch connected by data lines to the bit line sensors for latching the sensed voltage levels. Also provided is a means for preventing the formation of a conductor path to ground simultaneously through both the bit line sensors and the latch when the sensed voltage levels are latched. In preferred embodiments, means for isolating the bit lines from the data lines is provided.
By preventing formation of a conductor path to ground simultaneously through both the bit line sensing means and the latch means, current is not drawn in a fixed state. This reduces the operating power substantially. In providing bit line isolation, some speed is gained so that the overall speed of a memory device using the present invention is not significantly slower than one using a differential sense amplifier. In other words, the present invention sacrifices some speed in order to reduce operating power. However, the present invention is still faster than cross-coupled sense amplifier latches since the matrix cell devices attached to the bit lines must work against the cross-coupled sense amplifier latches.
Other objects, advantages, and novel features of the present invention will be become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.